The present invention generally relates to digital signal reproducing apparatuses, and more particularly to a digital signal reproducing apparatus which reproduces pre-recorded digital signals from a magnetic tape by use of rotary magnetic heads.
In a digital audio tape recorder, an analog audio signal is modulated into PCM audio data by a pulse code modulation (PCM), and the PCM audio data are recorded on and reproduced from a magnetic tape together with error detecting and correction codes and the like as PCM data. In a rotary head type digital audio tape recorder which employs rotary magnetic heads, data are successively recorded on and reproduced from tracks formed obliquely to a longitudinal direction of the magnetic tape without a guard band between two mutually adjacent tracks, alternately by a pair of rotary magnetic heads having gaps of mutually different azimuth angles. A tracking control signal (Automatic Track Find signal and hereinafter simply referred to as an ATF signal) is recorded on and reproduced from starting and ending portions of each track, while the PCM data are recorded and reproduced from an intermediate portion between the starting and ending portions of each track with a predetermined signal format.
The data are recorded on each track of the magnetic tape in blocks, and the starting and ending portions of the track are occupied by blocks of subcodes, the ATF signal and the like, while the intermediate portion (that is, the data region) between the starting and ending portions is occupied by blocks of the PCM data.
As will be described later in the present specification in conjunction with drawings, in a conventional digital signal reproducing apparatus, digital signals reproduced from the magnetic tape by the rotary magnetic heads are demodulated in a data demodulating circuit and are supplied to a random access memory (RAM). The data are also supplied to a synchronizing signal detector and block address reproducing circuit wherein a synchronizing signal and a block address is detected. The detected synchronizing signal and the block address are supplied to a write-in address control circuit. The write-in address control circuit operates a symbol address counter thereof by using the synchronizing signal as a reference and operates a block address counter thereof by using the block address as a reference, and the write-in address of the RAM is determined by outputs of these two address counters.
On the other hand, the reproduced digital signals are supplied to a tracking control signal detecting circuit which detects the ATF signal, and the detected ATF signal is supplied to a data region discriminating circuit. The data region discriminating circuit produces a data region discriminating signal by presuming from the ATF signal the region where the PCM data is recorded. The data region discriminating circuit determines the time period in which the synchronizing signal detector and block address reproducing circuit detects the synchronizing signal and the time period in which the write-in operation is carried out under the control of the write-in address control circuit.
However, the block address counter within the write-in address control circuit is designed to count from 0 to 392 blocks. Hence, when writing the PCM data reproduced from one track into the RAM, the counted value in the block address counter has already reached a predetermined value since the blocks of the subcode data, the ATF signal and the like are counted before the blocks of the PCM data. For this reason, in order to minimize unused addresses of the RAM and effectively utilize the memory capacity of the RAM, the output value of the block address counter must be decoded into a certain form. As a result, there is a problem in that a circuit is required exclusively for decoding the output value of the block address counter to the certain form.
Generally, the block address is loaded into the block address counter when the block address is correctly reproduced from the PCM data region. But since the counted value in the block address counter is already a predetermined value by the time the data are reproduced from PCM data region, it is necessary to add a certain value to the reproduced block address and load the added value to the block address counter. In other words, there is a problem in that a circuit is required exclusively for adding the certain value to the reproduced block address.
Furthermore, when producing the data region discriminating signal in the data region discriminating circuit, it is also necessary to generate timing signals by decoding an output value of a counter of the data region discriminating circuit. Hence, there is a problem in that a decoding circuit is required exclusively for decoding the output value of the counter in the data region discriminating circuit.
Therefore, the conventional digital signal reproducing apparatus suffers problems in that the circuit construction is complex due to the necessity to provide the circuits for decoding and adding.
On the other hand, a parity check circuit carries out a parity check on the demodulated reproduced data and supplies a load signal to the block address counter when no error is detected. However, a dropout may occur immediately after the reproduction of the synchronizing signal due to a scratch, dirt on the magnetic tape and the like. In addition, a data pattern identical to that of the synchronizing signal may occur due to a dropout. In these cases, there is a possibility that the parity check circuit will erroneously generate the load signal. When the parity check circuit erroneously generates the load signal, it is erroneously discriminated that no error exists in the block address, and the block address counter as a result outputs an erroneous block address. Therefore, there is a problem in that the PCM data will be written into erroneous addresses of the RAM.